ADT7476
Table 77. REGISTER 0X73 ? CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1)
Bit No.
[0]
[1]
[2]
[3]
[4]
[5]
[6]
Mnemonic
FanPresDT
Fan1Detect
Fan2Detect
Fan3Detect
AVG
ATTN
CONV
R/W
R/W
Read-only
Read-only
Read-only
R/W
R/W
R/W
Description
When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a 4-wire fan
on the appropriate TACH channel.
Fan1Detect = 1 indicates that a 4-wire fan is connected to the TACH1 input.
Fan2Detect = 1 indicates that a 4-wire fan is connected to the TACH2 input.
Fan3Detect = 1 indicates that a 4-wire fan is connected to the TACH3 input.
AVG = 1 indicates that averaging on the temperature and voltage measurements is turned
off. This allows measurements on each channel to be made much faster (x16).
ATTN = 1 indicates that the ADT7476 removes the attenuators from the +2.5 V IN , V CCP ,
+5.0 V IN , and +12 V IN inputs. These inputs can be used for other functions such as connecting
up external sensors. It is also possible to remove attenuators from individual channels using
Bits [7:4] of Configuration Register 4 (0x7D).
CONV = 1 indicates that the ADT7476 is put into a single-channel ADC conversion mode. In
this mode, the ADT7476 can be made to read continuously from one input only, for example,
Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:5] of
TACH1 minimum high byte register (0x55).
Bits [7:5], Register 0x55
000
001
010
011
100
101
110
111
2.5 V
V CCP
V CC (3.3 V)
5.0 V
12 V
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
[7]
Res
This bit is reserved and should not be changed.
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 78. REGISTER 0X74 ? INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT [7:0] = 0X00)
Bit No.
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Mnemonic
2.5 V/
THERM
V CCP
V CC
5.0 V
R1T
LT
R2T
OOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
2.5 V/THERM = 1 masks SMBALERT for out-of-limit conditions on the 2.5 V/THERM timer
channel.
V CCP = 1 masks SMBALERT for out-of-limit conditions on the V CCP channel.
V CC = 1 masks SMBALERT for out-of-limit conditions on the V CC channel.
5.0 V = 1 masks SMBALERT for out-of-limit conditions on the 5.0 V channel.
R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1 masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 0 when one or more alerts are generated in Interrupt Status Register 2, assuming all
the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is still asserted.
OOL = 1 when one or more alerts are generated in Interrupt Status Register 2, assuming all
the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is not asserted.
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